1. Field of the Invention
The present invention relates to a successive approximation A/D (analog-to-digital) converter for carrying out analog-to-digital conversion of a plurality of analog signals in a continuous scanning mode.
2. Description of Related Art
FIG. 8 is a block diagram showing a conventional A/D converter, in which the reference numeral 1 designates a selector for sequentially selecting in response to a select signal output from a controller 5 one of analog signals to be A/D converted; 2 designates a DAC (digital-to-analog converter) for generating a reference voltage in accordance with a value stored in a successive conversion register 4; 3 designates a comparator for comparing the reference voltage generated by the DAC 2 with the voltage of the analog signal selected by the selector 1; 4 designates the successive conversion register for storing a result of the comparison by the comparator 3; 5 designates the controller for producing the select signal and a control signal; and 6 designates a conversion result storing register for storing results of the A/D conversion.
Next, the operation of the conventional A/D converter will be described.
The A/D converter of FIG. 8 scans n analog signals sequentially so that they are converted into digital signals in order. For example, to achieve the A/D conversion of an analog signal AN0, the controller 5 supplies the selector 1 with the select signal instructing the A/D conversion of the analog signal AN0, and the selector 1 selects the analog signal AN0 in response to the select signal.
When supplying the selector 1 with the select signal, the controller 5 sets the most significant bit of the successive conversion register 4 to "1" (it corresponds to bit 7 in an 8-bit A/D converter, for example. The following description will be provided taking an 8-bit A/D converter as an example for convenience sake), and sets the remaining bits (from bit 6 to bit 0) to "0".
The DAC 2 generates, after the controller 5 sets the value of the successive conversion register 4, the reference voltage in accordance with the value stored in the successive conversion register 4, and the comparator 3 compares the reference voltage with the voltage of the analog signal selected by the selector 1.
If the voltage of the analog signal is equal to or greater than the reference voltage (voltage of the analog signal.gtoreq.reference voltage), the comparator 3 sets the most significant bit of the successive conversion register 4, the bit 7 to "1". In contrast, if the voltage of the analog signal is less than the reference voltage (voltage of the analog signal&lt;reference voltage), it sets the most significant bit of the successive conversion register 4, the bit 7 to "0".
After completing the conversion of the bit 7, the most significant bit, the controller 5 changes the bit 6 of the successive conversion register 4 from "0" to "1" (thus, the bit 7 is set at the conversion result, the bit 6 is set at "1" and the remaining bits 5-0 are set at "0"). Then, in the same manner as described above, the DAC 2 generates the reference voltage in accordance with the value stored in the successive conversion register 4, and the comparator 3 compares the reference voltage with the voltage of the analog signal selected by the selector 1.
If the voltage of the analog signal is equal to or greater than the reference voltage (voltage of the analog signal.gtoreq.reference voltage), the comparator 3 sets the bit 6 to "1". On the contrary, if the voltage of the analog signal is less than the reference voltage (voltage of the analog signal&lt;reference voltage), it sets the bit 6 to "0".
After completing the conversion of the bit 6 in this way, the converter carries out the conversion successively of the bits 5-0 in the same manner as described above. When the conversion of the bits 5-0 is completed, the A/D conversion of the analog signal AN0 is finished, and the value stored in the successive conversion register 4 is stored in the conversion result storing register 6.
Completing the A/D conversion of the analog signal AN0, the converter starts the conversion of the next analog signal AN1 as illustrated in FIG. 9. Thus, when there are n analog signals, the update period of each analog signal becomes as follows:
Update period=full bit conversion period.times.number of the analog signals=conversion period per bit.times.number of bits to be converted.times.number of analog signals
Besides the foregoing conventional example, Japanese patent application laid-open No. 5-14197/1993 discloses a technique, in which the converter compares the voltage of the current analog signal with the voltage of the previous analog signal, and carries out full bit A/D conversion only when they disagree with skipping the A/D conversion when they agree, thereby trying to reduce the update period of the analog signals.
With the arrangement as described above, the conventional A/D converter can convert the analog signal into the digital signal through the full bit conversion (for example, it carries out eight conversion processings in the 8-bit A/D converter). The conventional A/D converter, however, has a problem in that the update period of the analog signals will increase with the number of the bits of the A/D converter because of an increase in the number of conversions, thereby degrading tracking ability of the digital signals to the variations of the analog signals.